The present invention relates to data processing networks in which multiple processing devices share an interface to main storage, and more particularly to a process for testing hardware and microcode serialization mechanisms in such networks.
Among the recent trends in data processing are computer architectures which increasingly employ multiple processing devices sharing a common interface to main storage. Multiple processor networks typically employ serializing mechanisms in order to protect shared objects in main storage. In other words, should two or more of the processors simultaneously request access to a shared area of data within main storage, one or more of the serializing mechanisms resolves the conflict and grants access to one of the requesting processors.
While the testing of serialization mechanisms is desirable and necessary to insure their reliability, such testing requires conflicting requests for a main storage shared object to overlap within a single clock cycle, a situation which rarely occurs at random and is difficult to force. There is no observable difference between conflicting processor requests executing in parallel (and being properly serialized by the serializing mechanisms), and the same instructions executing in sequence.
The general idea of forcing a conflict between processors is known. For example, IBM Technical Disclosure Bulletin, Volume 17, No. 6 (November 1974) discloses a process for synchronizing two processing devices, one designated as the local device and the other, the remote device. The local and remote processors execute different instructions, toward putting both of them in a "null" state during the same clock cycle, so that both processing devices begin executing the next instruction simultaneously. If both processors seek the same storage location, a locking mechanism designed to allow access to only one of the processors is tested.
Various means are known for synchronizing processing devices, although not necessarily in connection with testing locks or other serializing mechanisms. For example, U.S. Pat. No. 4,412,303 (Barnes et al) discloses a system including an array of processors, memory modules, a network connecting the processors and the memory modules, and a data base memory with a data base memory controller. The system also includes a coordinator for synchronizing the processors when parallel operation of the processors is desired.
U.S. Pat. No. 4,783,736 (Ziegler et al) discloses a system for governing multiple processors connected in parallel to a plurality of interleaved memory elements, with memory access patterns designed to insure a desired offset of the patterns, to avoid access conflicts. Various master and slave processing devices operate under different codes.
While these means of synchronization and the aforementioned testing approach are each satisfactory under certain circumstances, there has remained a critical need for synchronizing multiple processing devices, and utilizing this synchronization to achieve repeatable conflicts, between and among the processors, for shared objects in main storage.
Therefore, it is an object of the present invention to provide a means for placing multiple processors into a hold (non-executing) state, and subsequently to simultaneously release all processors from the hold state or condition.
Another object of the invention is to provide a computer program synchronization instruction executed by multiple processors, each in turn, toward achieving the hold state, that operates identically regardless of the order in which the processors execute the instruction.
A further object is to provide a means for selectively interposing a delay on one or more selected processors, following the synchronization of all processors.
Yet another object is to provide a means for incrementing such delay associated with one or more chosen processors to increase the delay by a selected amount, for example a single clock cycle, each time the synchronization instruction is executed.